Circuit for evaluating signal timing
US6073261A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 22, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | May 22, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention is generally directed to a circuit and method for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with one aspect of the invention, a circuit is provided having a signal select circuit that is includes two or more inputs and one output. The signal select circuit (preferably a multiplexer) is configured to select one of the two or more input signals for evaluation and direct it to the output. A plurality of signal buffers are electrically cascaded to the output of the signal select circuit. Finally, a scan chain having a plurality of scan elements is disposed to acquire a state of electrical signals along the plurality of signal buffers. In accordance with another aspect of the invention, a method is provided for evaluating the timing relationship of electrical signals in an integrated circuit. In accordance with this inventive aspect, the method includes the steps of selecting a first electrical signal to be evaluated and discretizing the selected electrical signal into a plurality of signal values closely spaced in time. This "discretizing" function is preferably achieved passing the selected signal through a p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.