Turn-off circuit for an LDMOS in presence of a reverse current
US6075391A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0018
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for charging a capacitance using an LDMOS integrated transistor functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance. The LDMOS transistor is controlled via a bootstrap capacitor charged by a diode at the supply voltage of the circuit, and by an inverter driven by a logic control circuit as a function of a Low Gate Drive Signal and of a second logic signal which is active during a phase wherein the supply voltage is lower than the minimum switch-on voltage of the integrated circuit. The circuit uses a first zener diode to charge the bootstrap capacitor and the source of the transistor is connected to the supply node through a second zener diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.