Cancellation of injected charge in a bus switch
US6075400A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Aug 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/162
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor. The sources and drains of the compensating transistors are connected together so that they transistors act as capacitors. A connecting p-channel transistor is added in parallel with the main p-channel transistor. The connecting p-channel transistors is turned on early, before the main p-chann…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.