Method and circuit for data dependent voltage bias level
US6075476A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Nov 12, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1295
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the computer output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.