Method and apparatus for accelerating rendering by coalescing data accesses
US6075544A · kind A · utility
15Cited by
3References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Apr 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for accelerating processing of pixel data being provided to a frame buffer comprising circuitry for determining that pixel values vary linearly over a scan line of a polygon to be rendered, linear interpolation circuitry for providing pixel values using a process of linear interpolation between accurately determined pixel values, and a circuit for collecting pixel values to be written to a frame buffer until a significant number of pixel values may be written together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.