Method and apparatus for deskewing clock signals
US6075832A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Oct 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for deskewing clock signals in a synchronous digital system. The apparatus contains a phase detection circuit that receives a plurality of clock signals and generates an output based on a phase relationship between those clock signals. A controller then receives the output of the phase detector and determines which one of the plurality of clock signals requires adjustment based on the output of the phase detector and a bit from a delay shift register. The controller transmits a delay signal to one of a plurality of delay circuits which modifies the delay of the clock signal that the controller determined to require adjustment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.