Method and apparatus for counting signal transitions
US6075833A · kind A · utility
15Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Dec 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for counting events occurring between two different clock domains includes a gray code counter having at least two stages. The gray code counter is incremented by the event to be counted. Dual rank synchronizer circuit and delay flip/flops are coupled to the counter. The circuit includes a comparison logic circuit fed by outputs from the dual rank synchronizers and the delay flip/flops to produce an output signal having a binary value corresponding to a number of events that occurred between transitions of the second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.