Method for optimizing contact pin placement in an integrated circuit
US6075934A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | May 1, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing contact pin placement in an integrated circuit, wherein a netlist containing connectivity information, and placement information for a semiconductor circuit is read. Each net in the circuit is classified (510). Unblocked tracks are identified for each net in the circuit (512). All contact pins associated with nets having a power supply classification are placed according to a power supply location (513). The blockage for each remaining net is updated. Next, all contact pins for nets residing within a defined diffusion are placed (514) The blockage for each remaining net is updated. Next, all contact pins for nets residing in multiple defined diffusion areas are placed (515).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.