Multimedia computer architecture with multi-channel concurrent memory access
US6076139A · kind A · utility
203Cited by
12References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Sep 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system providing multiple processors or masters an architecture for highly concurrent processing and data throughput. A multiple channel memory architecture provides concurrent access to memory. Arbitration and snoop logic controls access to each memory channel and maintains cache coherency. A host CPU, multimedia processor, pipes processor and display controller may independently and concurrently access memory. The pipes processor provides a decoupled input/output processor for universal serial bus and firewire serial buses to free up the host CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.