Processor pipeline including partial replay
US6076153A · kind A · utility
24Cited by
12References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Dec 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention, in one embodiment, is a method for committing the results of at least two speculatively executed instructions to an architectural state in a superscalar processor. The method includes determining which of the speculatively executed instructions encountered a problem in execution, and replaying the instruction that encountered the problem in execution while retaining the results of executing the instruction that did not encounter the problem.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.