Shared register architecture for a dual-instruction-set CPU to facilitate data exchange between the instruction sets
US6076155A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30196
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction ad…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.