Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
US6076175A · kind A · utility
37Cited by
7References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of the chip reduces the amount of time required to test the chip to determine the acceptability of the chip and its actual bit error rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.