Compiling system and method for partially reconfigurable computing
US6077315A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/44521
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compiling system and method generates a sequence of program instructions for use in a partially reconfigurable processing unit, a portion of the processing unit having a hardware organization that is selectively reconfigurable during execution of the sequence of program instructions among a plurality of configurations, and a portion of the processing unit having a non-reconfigurable hardware organization, each configuration comprising a computational unit optimized for performing a class of computations. A compiler selectively compiles high-level source code statements for execution using configurations of the reconfigurable portion of the processing unit responsive to meta-syntax compiler directives. A linker creates object files that optionally encapsulate bitstreams specifying hardware organizations corresponding to the configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.