Semiconductor integrated circuit device having a short circuit preventing circuit
US6078096A · kind A · utility
9Cited by
11References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Oct 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
Abstract
A 16 Mbit DRAM of the invention is made up of a nexus of four 4 Mbit DRAM chips which are formed adjacent to one another on the wafer and each constitute an individual 4 Mbit DRAM, the connection between the 4 Mbit DRAMs is formed through a short-circuit protecting circuit provided within each 4 Mbit DRAM and an interconnection/controller circuit portion formed in the dicing area between the 4 Mbit DRAMs. When the nexus is cut along the dicing area containing the interconnection/controller circuit portion, 4 Mbit DRAM chips and/or 8 Mbit DRAM chips can be produced as desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.