Apparatus and method for providing a static mode for dynamic logic circuits
US6078193A · kind A · utility
9Cited by
8References
37Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Apr 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for providing a static mode for logic circuits with dynamic latches. The invention provides a reliable static mode for testing of the logic circuit, prevents "through current" power consumption when clocks to the logic circuit are stopped, and allows the circuit to be powered down when idle. The system includes a circuit for forcing clock phases to an active state, a circuit for breaking feedback paths within the logic circuit, and an optional clock loss detector for detecting clock inactivity and automatically initiating the static mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.