Display memory cache
US6078316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1995 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | May 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An optimized refresh strategy for increasing bandwidth of an LCD. The present invention results in an LCD suitable for dynamic display of information. In the present invention, a display memory is used to store display data generated by a CPU and to provide that data to an LCD. All data writes to the display memory by the CPU are tracked and rows or columns that contain modified data are tagged. These tags may be "set" by mapping the display memory write addresses to row or column numbers. The tags are examined and mapped back into the display memory addresses and only those rows or columns containing changed data are transferred to the data stream for display. As a result, only the information that is changed in the display memory is sent to the display and the dynamic bandwidth of the display is maximized. The refresh in the present invention can be either row-based or column-based.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.