Pipelined dual port integrated circuit memory
US6078527A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Jun 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.