Method and apparatus for improving performance of DRAM subsystems with SRAM overlays
US6078532A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 1999 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Feb 1, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2281
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system reducing or eliminating the effects of DRAM page-opening delays or row access delays is provided. The system uses DRAM and fast memory such as SRAM. SRAM is used to store the initial portions of data from data blocks and corresponding portions of DRAM are used to store the terminal portions of data from the data blocks. When access to a block of data is requested, DRAM row access procedures are initiated. During the delay period, while DRAM row access procedures are occurring, the initial portion of data from the requested block is read-out from SRAM. By about the time the initial data read-out from SRAM is completed, DRAM row access procedures are completed and the remaining portion of the data is read-out from DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.