Semiconductor memory having redundancy circuit

US6078534A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Karl-Peter Pfefferl · Hohenkirchen, DE
• Martin Gall · Kalamazoo, US

Key dates

• Filing date: Sep 25, 1997
• Grant date: Jun 20, 2000
• Expiry date: Sep 25, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/80
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory having an array of memory cells. The array includes a plurality of normal memory cells and a redundant memory cell. A decoder is provided for selecting an addressed one of the normal memory cells in response to an address and a normal condition signal and adapted address the redundant memory cell in response to the address and a fault condition signal. A redundant decoder is provided having an electronically erasable read-only-memory cell. The redundant decoder is adapted to produce the normal condition signal and to convert the normal condition signal into the fault condition signal when such read-only-memory cell is programmed into a fault condition. Each one of the read-only memory cells include a flash memory cell, a ferroelectric memory cell, or other such type of electronically erasable read-only memory cell which is substantially non-volatile and is able to retain its programmed state for a relatively long period of time. With such an arrangement, because the electronically erasable read-only-memory cell is electronically programmable, a defective normal memory cell may be replaced with a redundant memory cell the memory is packaged.