BiCMOS compacted logic array

US6081004A · kind A · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Anthony Wong · Cupertino, US
• Anna Tam · Cupertino, US
• Daniel Wong · San Jose, US

Key dates

• Filing date: Mar 27, 1995
• Grant date: Jun 27, 2000
• Expiry date: Mar 27, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/996

Abstract

A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.