Reduced size field effect transistor
US6081006A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Aug 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reduced size field effect transistor is disclosed which has a substrate with a body of semiconductor material having an active region on one surface thereof, and a common conductor located in remote insulated relation to the one surface of the semiconductor body, a pair of source electrodes, a drain electrode and a gate electrode located on the one surface, with the drain electrode having drain fingers located on opposite sides of each of the source electrodes and an air bridge overlying the source electrodes and interconnecting the drain fingers located on opposite sides of each of the source electrodes, the gate electrode having a connection pad at one side thereof and a manifold extending between the source electrodes, and having gate fingers extending between the drain fingers and the source electrodes, and conductive connections between the source electrodes and the common conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.