High voltage drive output buffer for low Voltage integrated circuits
US6081132A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Mar 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage drive output buffer for low voltage integrated circuits comprising a pullup pFET; a driver pFET having a source connected to the drain of the pullup pFET, and having a gate connected to a biasing circuit; a driver nFET having a drain connected to the drain of the driver pFET, and having a gate connected so as to be biased; and a pulldown nFET having a drain connected to the source of the driver nFET; wherein the pullup pFET and pulldown nFET are coupled to switch in complementary fashion in response to an input voltage; and wherein the biasing circuit comprises an nFET having a drain connected to the gate of the driver pFET and coupled to the input node so as to switch ON for a transitory period when the pullup pFET switches from OFF to ON.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.