Hold time margin increased semiconductor device and access time adjusting method for same
US6081142A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Mar 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A load adjusting circuit 36 adjusts the load value L=L2 of a dummy load circuit 31x corresponding to the outputs of a frequency determining circuit 37 and an interface determining circuit 35 as L2=L1-.DELTA.L holding, where L=L1 is a proper value in the case that the access time does not depend on the frequency of the data DQ and .DELTA.L corresponds to a half of the maximum value tlc of the deviation of the access time that varies corresponding to the frequency of the data DQ. A DLL circuit 40 delays a internal clock iCLK by a time .delta.tx so that a difference between phases of the clock iCLK and a dummy internal clock d.sub.-- iCLK becomes a predetermined value. The delay time .delta.tx is equal to a value determined in such a way that .delta.tx=67 tx0 is determined with activating the DLL circuit 40, tlc is determined and .delta.tx is finally determined as .delta.tx=.delta.tx0+ tlc/2 or .delta.tx=.delta.tx0-tlc/2 due to the condition of data frequency at determining .delta.tx0.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.