Signal change detection circuit
US6081144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Jul 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1534
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input signal SIN is input to a reset input terminal R of a flip-flop RSFF1 and, at the same time, input to a gate of a pMOS transistor MP1 constituting a transfer control circuit DCNTL1, a signal Bd obtained by delaying an inverted output signal B of the flip-flop RSFF1 at a delay circuit DLY1 is input to the data input terminal of the transfer control circuit DCNTL1, and the output signal of the transfer control circuit DCNTL1 is input to a set input terminal S of the flip-flop RSFF1 via two stages of inverters connected in series, therefore, a signal change detection circuit capable of generating a stable pulse according to the level change of the input signal without depending upon the input clock signal and capable of generating the pulse at high speed can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.