Low-power decimator for an oversampled analog-to-digital converter and method therefor
US6081216A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampled analog-to-digital converter (ADC) (20) includes a sigma-delta modulator (21) with two decimation filters to provide minimum power consumption. The first decimation filter (30) converts the output of the sigma-delta modulator (21) to a slower intermediate frequency and performs a first part of the decimation function. The second decimation filter (40) converts the output of the first decimation filter (30) to the output frequency and performs a second part of the decimation function. The ADC (20) saves power by allowing some of the second part of the decimation function to be performed at the slower intermediate frequency. In one form, the first decimation filter (30) includes a finite impulse response (FIR) filter (32) and a down sampler (34). By using a suitable logic circuit (56), the FIR filter (32) can be implemented with only a small amount of circuit area and most of the FIR filter (32) can be operated at the slower intermediate frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.