Power saving arrangement for a flash A/D converter
US6081219A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 5, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | May 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An arrangement for reducing power consumption in a flash A/D converter uses a predictor module to compute the "next" digital output value (i.e., s(n+1)) and then uses this value to regulate the number of individual comparators required to perform an accurate conversion. The predictor module is disposed as a feedback element between the converter output and the comparator array. Based upon the prediction, the module transmits a control signal to the comparator array, turning "on" and "off" subsets of the comparators forming the array. By maintaining a large number of the comparators in the "off" state (usually, only half of the comparators need to be enabled), a significant power savings can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.