Static RAM circuit for defect analysis
US6081465A · kind A · utility
16Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Small feature CMOS defect analysis of SRAM circuits is made less time consuming with the inclusion of an in-circuit test connection which is brought to external contact pads. External measurement and circuit forcing are accomplished via the external contact pads. A fault library for comparison to automated tests results provides faster resolution of process defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.