Method of testing clock paths and network elements for carrying out the method
US6081550A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The indicated test method makes it possible to test clock paths via which a reference clock is transmitted to synchronize network elements in a synchronous digital telecommunications system. To that end the reference clock is marked at the start of the clock path being tested by modulating information thereon. It is observed at the end of the clock path being tested whether the reference clock contains the information modulated thereon at the start. This information is configured so that it does not impair the operation of the synchronous digital telecommunications system. A network element is furthermore indicated, which is in a position to produce by itself the phase modulation required for a test, through its clock generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.