Parallel integrated frame synchronizer chip

US6081570A · kind A · utility

Assignee

• The United States of America as represented by the Administrator of the National Aeronautics and Space Administration · US

Inventors

• Parminder Singh Ghuman · Severn, US
• Jeffrey Solomon · Millbrae, US
• Toby D. Bennett · Adelphi, US

Key dates

• Filing date: Sep 2, 1997
• Grant date: Jun 27, 2000
• Expiry date: Sep 2, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/048
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A parallel integrated frame synchronizer which implements a sequential pipeline process wherein serial data in the form of telemetry data or weather satellite data enters the synchronizer by means of a front-end subsystem and passes to a parallel correlator subsystem or a weather satellite data processing subsystem. When in a CCSDS mode, data from the parallel correlator subsystem passes through a window subsystem, then to a data alignment subsystem and then to a bit transition density (BTD)/cyclical redundancy check (CRC) decoding subsystem. Data from the BTD/CRC decoding subsystem or data from the weather satellite data processing subsystem is then fed to an output subsystem where it is output from a data output port.