Method and apparatus for halting a processor and providing state visibility on a pipeline phase basis
US6081885A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Microprocessor 1 is operable to halt in response to an emulation event with partially completed instructions still in the execution pipeline. Thus, emulation unit 50 can provide visibility to the state of the microprocessor on a single pipeline phase basis. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring that could otherwise affect memories 22-23 or peripheral devices 60-61 during e…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.