Method and assembly for providing improved underchip encapsulation
US6083819A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jun 26, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microelectronic assembly (10) includes a printed circuit board (12) that includes a substrate (14) having a die attach region (22) and a plurality of first bond pads (24) disposed and spaced apart at the die attach region (22). A channel (26) effective in improving fluid flow extends across the die attach region (22) apart from the first bond pads (24). An integrated circuit die (16) is mounted onto the printed circuit board (12) and includes a major face (28) facing the substrate (14) and spaced apart therefrom by a gap (30) and second bond pads (25) disposed on the major face (28) in a pattern such that each of the second bond pads (25) registers with a first bond pad (24). Solder bump interconnections (18) connect the first bond pads (24) to the second bond pads (25). Encapsulant (20) is disposed within the gap (30) and flows over the substrate (14) and the channel (26) to encapsulate the solder bump interconnections (18). Channel 26 enhances the flow of the precursor (19) in the gap (30) prior to curing the precursor (19) to form the encapsulant (20).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.