Buffer driver reference circuit
US6084444A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for charging or discharging a capacitive load. The circuit includes a buffer driver comprising first and second input terminals and an output terminal, and a reference voltage generator coupled to the buffer driver. The reference voltage generator includes an enablement signal terminal, first and second reference voltage terminals, and a circuit operable to provide first and second reference voltages at the first and second reference voltage terminals in response to a first signal at the enablement terminal. The reference voltage generator also provides first and second rail voltages in response to a second signal at the enablement terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.