Clock duty cycle control technique
US6084452A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jun 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes a reference circuit and a comparison circuit. The reference circuit is coupled to a first node having the first voltage and a second node having the second voltage to generate a reference signal from the first and second voltages. The reference circuit includes at least one instance of a first electrical characteristic cell. The comparison circuit is coupled to receive a feedback clock signal and to generate a comparison signal therefrom. The comparison circuit includes at least one instance of the first electrical characteristic cell. The duty cycle error measurement circuit is coupled to receive the reference signal and the comparison signal. The duty cycle error measurement circuit rejects the common mode of the reference and comparison signals and passes the differential mode of the reference and comparison signals to generate a duty cycle adjust signal responsive to receiving the re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.