High-speed CMOS latch
US6084455A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 13, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Aug 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356113
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high-speed CMOS latch includes at each storage node a pull-up P-transistor with its gate tied to a dynamic node, and a pull-down N-transistor with its gate controlled by the inverse of the states of the remaining dynamic nodes. The P-transistor drives the storage node high to VDD, and the N-transistor drives the node low to VSS, as appropriate. During evaluation, one dynamic node discharges to a low state and in response each storage node is driven relatively quickly to the desired high or low state through either the associated pull-up or pull-down transistor. Precharging P-transistors drive the dynamic nodes high during precharge periods. As the dynamic nodes go high, they turn off all of the pull-up and pull-down transistors that drive the latch storage nodes, and the latch retains the evaluated state of the dynamic nodes until the start of the next evaluation cycle. Accordingly, the latch does not require a separate clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.