Offset calibration of a flash ADC array
US6084538A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jun 10, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method is disclosed for calibrating comparators of an ADC. Individual comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra "proxy" or replacement comparators. More particularly, at periodic intervals a psuedo-random one of the comparators may be disconnected from the standard ADC circuitry for calibration. In order to prevent a significant degradation in the conversion quality, the digital logic downstream of the comparators may be designed to provide the necessary adjustments to accommodate for the removal of one of the comparators. Thus, a calibration technique is provided in which individual comparators are removed from the data conversion path during conversion and the downstream logic adjusts to accommodate for the removal of the comparator. The calibration technique is particularly advantageous for use with optical data storage systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.