Hardware efficient digital channelized receiver
US6085077A · kind A · utility
26Cited by
4References
18Claims
0Family size
Inventors
Key dates
| Filing date | Jan 21, 1997 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jan 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0266
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
The present invention documents a digital channelized receiver for signal intercept applications. A hardware efficient implementation of a uniform filter bank in which the number of filters, K, is greater than the decimation factor, M, is provided. By optimizing the filter bank frequency response, in conjunction with K and M, the proposed invention allows a simple channel arbitration logic to be implemented. In addition, the present invention provides reliable instantaneous frequency measurements and parameter estimates across the desired frequency range while reducing the data processing speed requirements by a factor of M.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.