Monitoring processor execution cycles to prevent task overrun in multi-task, hard, real-time system
US6085218A · kind A · utility
51Cited by
7References
8Claims
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Key dates
| Filing date | Jul 13, 1994 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jul 13, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hard, real-time, multi-tasking system is monitored by combined hardware and software and logic to detect overrun of any task beyond a declared maximum processor cycle limit for the task. Processor execution cycles utilized by DMA or interrupt processing and not related to the task being executed are not counted. Counter hardware and control logic reduces software overhead for monitoring execution cycle utilization by a task and provides capability not only of overrun detection, but programmed cycle usage alarm, consumed cycle count and overall processor loading or utilization measurements to be made.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.