System bus arbitrator for facilitating multiple transactions in a computer system
US6085271A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus using, in one embodiment, a multiple split mode for issuing multiple read or write requests that may be used during a data transaction within a computer system. In one embodiment, a processing unit comprises a bus arbitrator having bus control lines for controlling a bus, which transmits address and data information. The arbitrator is capable of issuing multiple consecutive read or write requests including at least one read request on the bus without releasing control by the processing unit over the bus during the consecutive read or write requests. In addition, the arbitrator is also designed to abort consecutive read requests during address cycles in response to bus control lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.