Method of and apparatus for validating data read out of a multi port internally cached dynamic random access memory (AMPIC DRAM)
US6085290A · kind A · utility
74Cited by
6References
8Claims
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Key dates
| Filing date | Mar 10, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Mar 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/3042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for and method of enhancing the performance of a multi-port internal cached DRAM (AMPIC DRAM) by providing an internal method of data validation within the AMPIC memories themselves to guarantee that only valid requested data is returned from them, or properly marked invalid data. A modified technique for identifying bad data that has been read out of AMPIC memory devices in the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.