Layered counterflow pipeline processor with anticipatory control
US6085316A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jul 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8053
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.