Area-efficient integrated self-timing power start-up reset circuit with delay of the start-up reset until the system clock is stabilized
US6085327A · kind A · utility
18Cited by
9References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and a method are disclosed for a power start-up reset circuit which is self-timing and which can be fully integrated in a standard CMOS or BiCMOS process along with other digital circuits. The circuit provides a system reset signal which is issued only after all circuit have stabilized by making the issuance of this system reset signal dependent on an oscillator becoming stable and a subsequent count of a fixed number of system clock cycles derived from that oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.