Fabrication method of lateral double diffused MOS transistors
US6087232A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Aug 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
According to a method for manufacturing double RESURF (reduced SURface Field) LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, on-resistance of double RESURF LDMOS transistors has been improved by using a new tapered p top layer on the surface of the drift region of the transistor, thereby decreasing the length of the drift region. Another advantage of the current invention is that the breakdown voltage similar with the on-resistance can be improved by using a reproducible tapered TEOS oxide by use of a multi-layer structure and low temperature annealing process. This is due to the reducing of the current path and impurity segregation in the drift region by using the tapered TEOS oxide instead of LOCOS filed oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.