DRAM cell configuration and method for its fabrication

US6087692A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernd Gobel · Dresden, DE
• Emmerich Bertagnolli · Munich, DE

Key dates

• Filing date: Jun 8, 1998
• Grant date: Jul 11, 2000
• Expiry date: Jun 8, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

A DRAM cell, including memory cells each having a first transistor, a second transistor and a third transistor. The memory cells also have a writing bit line, a writing word line, a read-out word line and a read-out bit line. The first transistor has a gate electrode and a second source/drain region. The second transistor has a gate electrode, a first source/drain region, and a second source/drain region. The gate electrode of the first transistor is connected to the first source/drain region of the second transistor. The second source/drain region of the second transistor is connected to said writing bit line. The gate electrode of the second transistor is connected to the writing word line. The third transistor has a gate electrode, a first source/drain region, and a second source/drain region. The gate electrode of the third transistor is connected to the read-out word line. The second source/drain region of the first transistor is connected to the first source/drain region of the third transistor. The second source/drain region of the third transistor is connected to the read-out bit line. The first, second and third transistors are vertical MOS transistors. The invention also …