Clock signal phase comparator
US6087857A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 3, 1997 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Oct 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock signal phase comparator includes a first delay unit for delaying a clock signal for a predetermined time, a first phase detector for comparing an output signal of the first delay unit and a reference clock signal and outputting a first high or low level output signal, a second delay unit for delaying for a predetermined time and outputting the reference clock signal, and a second phase detector for comparing an output signal of the second delay unit and the clock signal and outputting a second high or low level output signal. The phase comparator separately displays the phase comparison results in grades of fast, slow and locking, and when a locked phase is detected, the phase control system is partially or entirely disabled, for thereby reducing current consumption of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.