Hybrid dual threshold transistor multiplexer
US6087886A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 8, 1999 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Apr 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention deals with various circuits using transistors having two different threshold voltages designated high threshold voltage (HVT) and low threshold voltage (LVT). These circuits employ the know faster response time of LVT transistors while substantially avoiding the known greater leakage current of LVT transistors. A two input multiplexer includes two transmission gates driven in opposite phases by a selection control signal. One transmission gate, preferably the transmission gate most often selected, includes LVT transistors while the other transmission gate includes HVT transistors. A hybrid threshold voltage D flip-flop circuit employs LVT transistors in input transmission gates of both a master latch and a slave latch. In a conventional circuit, the output invertor of the slave latch also includes LVT transistors. In a split slave dual path circuit, the intermediate inverter also includes LVT transistors. In a push-pull output register, the inverter and transmission gate of the push-pull circuit may include LVT transistors. In a first alternative, only the transmission gates in the push-pull circuit and the slave latch include LVT transistors. In a second alternative…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.