Low power precision current reference
US6087894A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Mar 2, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/262
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.