Low capacitance chip varistor and fabrication method thereof
US6087923A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01C7/112
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A low capacitance chip varistor and a fabrication method thereof are described, which are capable of protecting the electronic elements of an electronic instrument from an external and internal surge and being well applicable to an electronic element which requires a low capacitance, and the low capacitance chip varistor includes at least one sheet support layer formed of a member having a low dielectric constant, a varistor layer including at least more than one varistor coating layer formed on the support layer, at least more than two internal electrode folded with a predetermined portion of the varistor layer to be connected with the varistor layer, one end of each of which is extended from a lateral surface of the support layer, and a pair of integrally formed external electrodes formed on a lateral surface of a varistor stack member integrally formed of the support layer, the varistor layer and the internal electrodes to be connected with one end portion of each internal electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.