Host DMA through subsystem XY processing
US6088046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1997 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Oct 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.