Data output system
US6088272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Oct 23, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a plurality of output buffers each of which outputs one of a plurality of one-bit signals forming data. The output buffers are put into a plurality of buffer groups. The memory system further includes a controller for feeding timing signals to the corresponding buffer groups via delay circuits having mutually different time constants, respectively. The timing signals include certain timing which causes the output buffers to output the corresponding one-bit signals. Since the foregoing certain timing is delayed depending on the time constants of the delay circuits, although the output buffers in the same buffer group output the corresponding one-bit signals simultaneously, the output buffers in the different buffer groups output the corresponding one-bit signals with mutually different timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.