Semiconductor memory device capable of preventing noise from occurring in the bus lines
US6088283A · kind A · utility
10Cited by
3References
46Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1998 |
| Grant date | Jul 11, 2000 |
| Priority date | — |
| Expiry date | Apr 13, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory, in order to eliminate unbalance of the coupling capacitance between a bit line and a bus line so as to prevent noises from occurring, a layer of a column selection signal line is disposed in an intermediate layer position between a layer of the bit line and a layer of the bus line. Also, the width of the column selection line is increased to cover the bit lines whose width are different from each other due to a contact, to thereby shield the bit line and the bus line by the column selection signal line, and to balance of the coupling capacitance between the bit line and the bus line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.